Q.1 The
NAND gate output will be low if the two inputs
are
The
(Conversion from Decimal number to
(Conversion
Ans:
A ring counter consisting of Five
15 ns because in synchronous counter all the flip-flops change state
Ans:
Ans:
Ans:
Ans:
Ans:
Ans:

NAND gate output will be low if the two inputs
are
(A) 00
(B) 01
(B) 01
(C) 10
(D) 11
(D) 11
Ans: D
The NAND gate output will be low if the two
inputs are 11 (The Truth Table of NAND gate is shown in Table.1.1)
inputs are 11 (The Truth Table of NAND gate is shown in Table.1.1)
X(Input)
|
Y(Input)
|
F(Output)
|
0
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
0
|
Table 1.1 Truth Table for NAND Gate
Q.2 What
is the binary equivalent of the decimal number
368
(A) 101110000
(B) 110110000
(B) 110110000
(C) 111010000
(D) 111100000
(D) 111100000
Ans: A
The
Binary equivalent of the Decimal number 368 is 101110000
(Conversion from Decimal number to
Binary number is given in Table 1.2)
2
|
368
|
2
|
184 — 0
|
2
|
92
— 0 |
2
|
46
— 0 |
2
|
23
— 0 |
2
|
11
— 1 |
2
|
5
— 1 |
2
|
2
— 1 |
2
|
1
— 0 |
0
— 1 |
Table 1.2 Conversion from Decimal number to Binary number
Q.3
Q3.The decimal equivalent of hex number 1A53 is
Q3.The decimal equivalent of hex number 1A53 is
(A) 6793 (B) 6739
(C) 6973 (D) 6379
Ans: B
The decimal equivalent of Hex Number 1A53 is 6739
(Conversion
from Hex Number to Decimal Number is given below)
1
|
A
|
5
|
3
|
Hexadecimal
|
16³
|
16²
|
16¹
|
16°
|
Weights
|
(1A53)16 = (1X16³) + (10 X 16²) + (5 X 16¹) + (3 X 16º)
= 4096 + 2560 + 80 + 3
= 6739
Q.4 (734)8 = ( )16
(A) C 1 D (B) D C 1
(C) 1 C D (D) 1 D C
Ans:
D
(734)8 = (1 D C)16
0001 | 1101 | 1100
1 D
Q.5 The number of control lines for a 8 – to – 1 multiplexer is
(A) 2 (B) 3
(C) 4 (D) 5
Ans: B
The number of control lines for an 8 to 1 Multiplexer is 3
(The control signals are used to steer any one of the 8 inputs to the
output)
output)
Q.6 How many Flip-Flops are required for mod–16 counter?
(A) 5 (B) 6
(C) 3 (D) 4
Ans: D
The number of flip-flops is required for Mod-16 Counter is 4.
(For Mod-m Counter, we need N
flip-flops where N is chosen to be the smallest number for which 2N is greater
than or equal to m. In this case 24
greater than or equal to 1)
flip-flops where N is chosen to be the smallest number for which 2N is greater
than or equal to m. In this case 24
greater than or equal to 1)
Q.7
EPROM contents can be erased by exposing
it to
EPROM contents can be erased by exposing
it to
(A)
Ultraviolet rays. (B) Infrared rays.
Ultraviolet rays. (B) Infrared rays.
(C) Burst of microwaves. (D) Intense heat radiations.
Ans: A
EPROM contents can be erased by exposing it to Ultraviolet rays
(The Ultraviolet light passes
through a window in the IC package to the EPROM chip where it releases stored
charges. Thus the stored contents are
erased).
through a window in the IC package to the EPROM chip where it releases stored
charges. Thus the stored contents are
erased).
Q.8 The hexadecimal number ‘A0’ has the decimal value equivalent to
(A) 80 (B) 256
(C) 100 (D) 160
Ans: D
The hexadecimal number
‘A0’ has the decimal value equivalent to 160
( A 0
‘A0’ has the decimal value equivalent to 160
( A 0
161 160 = 10X161 + 0X160 = 160
Q.1
Q.9 The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either
(A)
a NAND or an EX-OR (B) an OR or an EX-NOR
a NAND or an EX-OR (B) an OR or an EX-NOR
(C) an
AND or an EX-OR (D) a NOR or an EX-NOR
AND or an EX-OR (D) a NOR or an EX-NOR
Ans: D
The output of a logic gate is 1 when all inputs are at logic 0. The
gate is either a NOR or an EX-NOR .
gate is either a NOR or an EX-NOR .
Q.14
Data can be changed from special code to temporal code by using
Data can be changed from special code to temporal code by using
(A)
Shift registers (B) counters
Shift registers (B) counters
(C) Combinational circuits (D) A/D converters.
Ans: A
Data can be changed from special code to temporal
code by using Shift Registers.
(A Register in which data gets shifted towards left or right when clock pulses
are applied is known as a Shift Register.)
code by using Shift Registers.
(A Register in which data gets shifted towards left or right when clock pulses
are applied is known as a Shift Register.)
Q.15
A ring counter consisting of five Flip-Flops will have
A ring counter consisting of five Flip-Flops will have
(A)
5 states (B) 10
states
5 states (B) 10
states
(C) 32 states (D) Infinite states.
Ans: A
A ring counter consisting of Five
Flip-Flops will have 5 states.
Q.16
The speed of conversion is maximum in
The speed of conversion is maximum in
(A)
Successive-approximation A/D converter.
Successive-approximation A/D converter.
(B)
Parallel-comparative A/D converter.
Parallel-comparative A/D converter.
(C)
Counter ramp A/D converter.
Counter ramp A/D converter.
(D)
Dual-slope A/D converter.
Dual-slope A/D converter.
Ans: B
The speed of conversion is maximum in Parallel-comparator A/D
converter
converter
(Speed of
conversion is maximum because the comparisons of the input voltage are carried
out simultaneously.)
conversion is maximum because the comparisons of the input voltage are carried
out simultaneously.)
Q.17
The 2’s complement of the number 1101101 is
The 2’s complement of the number 1101101 is
(A) 0101110 (B) 0111110
(C) 0110010 (D) 0010011
Ans: D
The 2’s complement of the number 1101101 is 0010011 (1’s complement of
the number 1101101 is 0010010
the number 1101101 is 0010010
2’s complement of the number
1101101is 0010010 + 1 =0010011)
1101101is 0010010 + 1 =0010011)
Q.18
The correction to be applied
in decimal adder to the generated sum is
The correction to be applied
in decimal adder to the generated sum is
(A) 00101 (B) 00110
(C) 01101 (D) 01010
Ans: B
The correction to be applied in decimal
adder to the generated sum is 00110.
adder to the generated sum is 00110.
When the four
bit sum is more than 9 then the sum is invalid. In such cases, add
+6(i.e. 0110) to the four bit sum to
skip the six invalid states. If a carry is generated when adding 6, add the
carry to the next four bit group .
bit sum is more than 9 then the sum is invalid. In such cases, add
+6(i.e. 0110) to the four bit sum to
skip the six invalid states. If a carry is generated when adding 6, add the
carry to the next four bit group .
Q.19
When simplified with Boolean Algebra (x + y)(x + z) simplifies to
When simplified with Boolean Algebra (x + y)(x + z) simplifies to
(A)
x (B) x + x(y + z)
x (B) x + x(y + z)
(C) x(1 + yz) (D) x + yz
Ans: D
When simplified with Boolean Algebra (x + y)(x + z) simplifies to x +
yz [(x + y) (x + z)] = xx + xz + xy + yz
= x + xz + xy + yz ( xx = x)
yz [(x + y) (x + z)] = xx + xz + xy + yz
= x + xz + xy + yz ( xx = x)
= x(1+z) + xy + yz = x + xy +
yz { (1+z) = 1}
yz { (1+z) = 1}
= x(1 + y) + yz = x + yz { (1+y) = 1}]
Q.20
The gates required to build a half adder are
The gates required to build a half adder are
(A)
EX-OR gate and NOR gate (B) EX-OR gate and OR gate
EX-OR gate and NOR gate (B) EX-OR gate and OR gate
(C) EX-OR
gate and AND gate (D) Four NAND gates.
gate and AND gate (D) Four NAND gates.
Ans: C
The gates required to build a half adder are EX-OR gate and AND gate
Q.21 The code where
all successive numbers
differ from their
preceding number by single bit is
all successive numbers
differ from their
preceding number by single bit is
(A)
Binary code. (B) BCD.
Binary code. (B) BCD.
(C) Excess – 3. (D) Gray.
Ans: D
The code where all successive numbers
differ from their preceding number by single bit is Gray Code.
differ from their preceding number by single bit is Gray Code.
(It is an unweighted code. The most
important characteristic of this code is that only a single bit change occurs
when going from one code number to next.)
important characteristic of this code is that only a single bit change occurs
when going from one code number to next.)
Q.22 Which of the following is the
fastest logic
fastest logic
(A)
TTL (B) ECL
TTL (B) ECL
(C) CMOS (D) LSI
Ans: B
ECL is the fastest logic family of all
logic families.
logic families.
(High speeds
are possible in ECL because the transistors are used in difference amplifier configuration, in which they are
never driven into saturation and thereby the storage time is eliminated.
are possible in ECL because the transistors are used in difference amplifier configuration, in which they are
never driven into saturation and thereby the storage time is eliminated.
Q.23 If the input to T-flipflop is 100 Hz signal, the final output of the
three T-flipflops in cascade is
three T-flipflops in cascade is
(A) 1000 Hz (B) 500 Hz
(C) 333 Hz (D) 12.5 Hz.
Ans: D
If the input to T-flip-flop is 100 Hz signal,
the final output
of the three
T- flip-flops in cascade is 12.5 Hz
the final output
of the three
T- flip-flops in cascade is 12.5 Hz
Q.24 Which of the memory is volatile memory
(A)
ROM (B) RAM
ROM (B) RAM
(C) PROM (D) EEPROM
Ans: B
RAM is a volatile memory (Volatile
memory means the contents of the RAM get erased as soon as the power
goes off.)
memory means the contents of the RAM get erased as soon as the power
goes off.)
Q.25
|
-8 is equal to signed binary number
|
|
|
(A) 10001000
|
(B) 00001000
|
|
(C) 10000000
|
(D) 11000000
|
Ans: A
– 8 is equal to signed binary number 10001000
Q.26
DeMorgan’s first theorem shows the equivalence of
DeMorgan’s first theorem shows the equivalence of
(A) OR gate and Exclusive OR gate.
(B)
NOR gate and Bubbled AND gate.
NOR gate and Bubbled AND gate.
(C) NOR gate and NAND gate.
(D) NAND gate and NOT gate
Ans: B
DeMorgan’s first theorem shows
the equivalence of NOR gate and Bubbled AND gate
the equivalence of NOR gate and Bubbled AND gate
Q.27
The digital logic family which has the lowest propagation delay time is
The digital logic family which has the lowest propagation delay time is
(A)
ECL (B) TTL
ECL (B) TTL
(C) CMOS (D) PMOS
Ans: A
The digital logic family which has the lowest propagation delay time
is ECL
is ECL
(Lowest
propagation delay time is possible in ECL because the transistors are used in
difference amplifier configuration, in which they are never driven into
saturation and thereby the storage time is eliminated).
propagation delay time is possible in ECL because the transistors are used in
difference amplifier configuration, in which they are never driven into
saturation and thereby the storage time is eliminated).
Q.28
The device which changes from serial data to parallel data is
The device which changes from serial data to parallel data is
(A) COUNTER (B) MULTIPLEXER
(C) DEMULTIPLEXER (D) FLIP-FLOP
Ans: C
The device which changes from serial data to parallel data is
demultiplexer.
demultiplexer.
(A demultiplexer takes in data
from one line and directs it to any of its N outputs depending on the status of
the select inputs.)
from one line and directs it to any of its N outputs depending on the status of
the select inputs.)
Q.29
A device which converts BCD to Seven Segment is called
A device which converts BCD to Seven Segment is called
(A)
Encoder (B) Decoder
Encoder (B) Decoder
(C) Multiplexer (D) Demultiplexer
Ans: B
A device which converts BCD to Seven
Segment is called DECODER.
Segment is called DECODER.
(A decoder coverts binary words into alphanumeric
characters.)
characters.)
Q.30
In a JK Flip-Flop, toggle means
In a JK Flip-Flop, toggle means
(A) Set Q = 1 and Q = 0.
(B)
Set Q = 0 and Q = 1.
Set Q = 0 and Q = 1.
(C) Change the output to the
opposite state.
opposite state.
(D) No change in output.
Ans: C
In a JK Flip-Flop, toggle means Change the output to the opposite
state.
Q.31 The access time of ROM using bipolar transistors is about
(A)
1 sec (B) 1 msec
1 sec (B) 1 msec
(C) 1 µsec (D) 1 nsec.
Ans: C
The access time of ROM using bipolar transistors is about 1 m sec.
Q.32
The A/D converter
whose conversion time is independent of the number
of bits is
The A/D converter
whose conversion time is independent of the number
of bits is
(A) Dual slope (B) Counter type
(C) Parallel conversion (D) Successive approximation.
Ans: C
The A/D converter whose conversion time is independent of the Number
of bits is Parallel conversion.
of bits is Parallel conversion.
(This type uses an array of comparators connected in parallel and
comparators compare the input voltage at a particular ratio of the reference
voltage).
comparators compare the input voltage at a particular ratio of the reference
voltage).
Q.3When signed numbers are used in binary arithmetic, then which one of
the following notations would have unique representation for zero.
the following notations would have unique representation for zero.
(A) Sign-magnitude. (B) 1’s complement.
(C) 2’s complement. (D) 9’s complement.
Ans: A
Q.38 A 4-bit synchronous counter uses flip-flops with propagation delay
times of 15 ns each. The maximum possible time required for change of state
will be
times of 15 ns each. The maximum possible time required for change of state
will be
(A) 15 ns. (B) 30 ns.
(C) 45 ns. (D) 60 ns.
Ans: A
15 ns because in synchronous counter all the flip-flops change state
at the same time.
Q.39 Words having 8-bits are to be stored into computer memory. The number
of lines required for writing into memory are
of lines required for writing into memory are
(A) 1. (B) 2.
(C) 4. (D) 8.
Ans: D
Because 8-bit words required 8
bit data lines.
bit data lines.
Q.40 In successive-approximation A/D converter, offset
voltage equal to D/A converter’s
output. This is done to
voltage equal to D/A converter’s
output. This is done to
(A) Improve the speed of operation.
(B)
Reduce the maximum quantization error.
Reduce the maximum quantization error.
(C)
Increase the number of bits at the
output.
Increase the number of bits at the
output.
(D)
Increase the range of input voltage that can be converted.
Increase the range of input voltage that can be converted.
Ans: B
Q.41
The decimal equivalent of Binary number 11010 is
The decimal equivalent of Binary number 11010 is
(A) 26. (B) 36.
(C) 16. (D) 23.
Ans: A
11010 = 1 X 24 + 1 X 2 3 + 0 X 22 + 1 X 21 = 26
1 LSB
is added to the 2
is added to the 2
Q.42
1’s complement representation of decimal number
of -17 by using
8 bit representation is
1’s complement representation of decimal number
of -17 by using
8 bit representation is
(A) 1110 1110 (B) 1101 1101
(C) 1100 1100 (D) 0001 0001
Ans: A
(17)10
= (10001)2
= (10001)2
In 8 bit = 00010001
1’s Complement = 11101110
Q.43 The excess 3 code of decimal number 26
is
is
(A) 0100 1001 (B) 01011001
(C) 1000 1001 (D) 01001101
Ans: B
(26)10
in BCD is ( 00100110 ) BCD
in BCD is ( 00100110 ) BCD
Add 011 to each BCD 01011001 for excess – 3
Q.44 How many AND gates are required to realize Y = CD+EF+G
(A) 4 (B) 5
(C) 3 (D) 2
Ans: D
To realize Y = CD + EF + G
Two AND gates are required (for CD & EF).
Q.45 How many select lines will a 16 to 1 multiplexer will have
(A) 4 (B) 3
(C) 5 (D) 1
Ans: A
In 16 to 1 MUX four select
lines will be required to select 16 ( 24 ) inputs.
lines will be required to select 16 ( 24 ) inputs.
Q.46 How many flip flops are required to construct a decade counter
(A) 10 (B) 3
(C) 4 (D) 2
Ans: C
Decade counter counts 10 states from 0 to 9 ( i.e. from 0000 to 1001 )Thus four FlipFlop’s are required.
Q.47 Which TTL logic gate is used for wired
ANDing
(A)
Open collector output (B) Totem Pole
Open collector output (B) Totem Pole
(C) Tri state output (D) ECL gates
Ans: A
Open collector output.
Q.48
|
CMOS circuits consume power
|
|
|
(A) Equal to TTL
|
(B) Less than TTL
|
|
(C) Twice of TTL
|
(D) Thrice of TTL
|
Ans: B
As in CMOS one device is ON & one is Always OFF so power
consumption is low.
consumption is low.
Q.49
In a RAM, information can be stored
In a RAM, information can be stored
(A)
By the user, number of times.
By the user, number of times.
(B)
By the user, only once.
By the user, only once.
(C)
By the manufacturer, a number of times.
By the manufacturer, a number of times.
(D)
By the manufacturer only once.
By the manufacturer only once.
Ans: A
RAM is used by the user, number of times.
Q.52 The chief reason
why digital computers
use complemented subtraction is that it
(A)
Simplifies the circuitry.
Simplifies the circuitry.
(B)
Is a very simple process.
Is a very simple process.
(C)
Can handle negative numbers easily.
Can handle negative numbers easily.
(D)
Avoids direct subtraction
Avoids direct subtraction
Ans:
C
Using complement method negative numbers can also be subtracted.
Q.53
In a positive logic system, logic state 1 corresponds to
In a positive logic system, logic state 1 corresponds to
(A)
positive voltage (B) higher voltage level
positive voltage (B) higher voltage level
(C) zero voltage level (D) lower
voltage level
voltage level
Ans: B
We decide two
voltages levels for positive digital logic. Higher voltage represents logic 1
& a lower voltage represents logic 0.
voltages levels for positive digital logic. Higher voltage represents logic 1
& a lower voltage represents logic 0.
Q.54 The commercially available 8-input multiplexer integrated circuit in the TTL family
is
is
(A) 7495. (B) 74153.
(C) 74154. (D) 74151.
Ans: B
MUX integrated circuit in TTL is 74153.
Q.55 CMOS circuits are extensively used for ON-chip
computers mainly because
of their extremely
computers mainly because
of their extremely
(A)
low power dissipation. (B) high noise immunity.
low power dissipation. (B) high noise immunity.
(C) large packing density. (D) low cost.
Ans: C
Because CMOS circuits have large packing density.
Q.56
The MSI chip 7474 is
The MSI chip 7474 is
(A)
Dual edge triggered JK flip-flop (TTL).
Dual edge triggered JK flip-flop (TTL).
(B)
Dual edge triggered D flip-flop (CMOS).
Dual edge triggered D flip-flop (CMOS).
(C)
Dual edge triggered D flip-flop (TTL).
Dual edge triggered D flip-flop (TTL).
(D)
Dual edge triggered JK flip-flop (CMOS).
Dual edge triggered JK flip-flop (CMOS).
Ans: C
MSI chip 7474 dual edge triggered D Flip-Flop.
Q.57
Which of the following memories stores the most number of bits
Which of the following memories stores the most number of bits
(A) a 5M´ 8 memory. (B) a
1M ´ 16 memory.
1M ´ 16 memory.
(C) a 5M ´ 4 memory. (D) a
1M ´12 memory.
1M ´12 memory.
Ans:
A
5Mx8 = 5 x 220 x 8 = 40M (max)
Q.58
The process of entering data into a ROM is called
The process of entering data into a ROM is called
(A)
burning in the ROM (B) programming the ROM
burning in the ROM (B) programming the ROM
(C) changing the ROM (D) charging the ROM
Ans: B
The process of entering data into ROM is known as programming the ROM.
Q.59
When the set of input data to an even parity generator is 0111, the output will be
When the set of input data to an even parity generator is 0111, the output will be
(A) 1 (B) 0
(C) Unpredictable (D) Depends on the previous input
Ans:
B
In even parity generator if
number of 1 is odd then output will be zero.
number of 1 is odd then output will be zero.
Q.60
The number 140 in octal is equivalent
to
The number 140 in octal is equivalent
to
(A) (96)10 . (B) (86)10 .
(C) (90)10 . (D) none of these.
Ans: A
(140)8 = (96)10
1 x 82 + 4 x 8 + 0x 1 = 64
+ 32 = 96
+ 32 = 96
Q.61
The NOR gate output will be low if the two inputs are
The NOR gate output will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11
Ans: B, C, or D
O/P is low if any of the I/P is high
Q.62
Which of the following is the fastest
logic?
Which of the following is the fastest
logic?
(A) ECL (B) TTL
(C) CMOS (D) LSI
Ans: A
Q.63
How many flip-flops are
required to construct mod 30 counter
How many flip-flops are
required to construct mod 30 counter
(A) 5 (B) 6
(C) 4 (D) 8
Ans:
A
Mod – 30 counter +/- needs 5 Flip-Flop as 30 < 25 Mod – N counter counts total ‘ N ‘ number of
states.
states.
To count ‘N’ distinguished states we need
minimum n FlipFlop’s as [N = 2n] For eg. Mod
8 counter requires 3 Flip-Flop’s (8 = 23)
minimum n FlipFlop’s as [N = 2n] For eg. Mod
8 counter requires 3 Flip-Flop’s (8 = 23)
Q.64 How many address bits are required to represent a 32 K memory
(A)
10 bits. (B) 12 bits.
10 bits. (B) 12 bits.
(C) 14 bits. (D) 16 bits.
Ans:
D
32K = 25 x 210 = 215,
Thus 15 address bits are required, Only 16 bits can address it.
Q.65 The number of control lines for 16 to 1 multiplexer is
(A) 2. (B) 4.
(C) 3. (D) 5.
Ans:
B
As 16 = 24, 4 Select lines are
required.
required.
Q.66 Which of following requires refreshing?
(A)
SRAM. (B) DRAM.
SRAM. (B) DRAM.
(C) ROM. (D) EPROM.
Ans: B
Q.67 Shifting a register
content to left by one bit position
is equivalent to
content to left by one bit position
is equivalent to
(A)
division by two. (B) addition by two.
division by two. (B) addition by two.
(C) multiplication by two. (D) subtraction by two.
Ans:C
Q.68
For JK flip flop with J=1, K=0, the output
after clock pulse will be
For JK flip flop with J=1, K=0, the output
after clock pulse will be
(A) 0. (B) 1.
(C) high impedance. (D) no change.
Ans: B
Q.69
Convert decimal 153 to octal.
Equivalent in octal will be
Convert decimal 153 to octal.
Equivalent in octal will be
(A) (231)8 . (B) (331)8 .
(C) (431)8 . (D) none of these.