Here we providing analog and digital electronics mostly asked questions and answer PDF with solution.These questions have asked may times in various exam.For full questions please download full PDF,Due to lots of figures we will not able to post all questions here so some questions from PDF are following—.
Q.4 In applications where measurement of a physical quantity is involved, the OPAMP circuit
recommended is
(A) Basic non-inverting amplifier (B) A comparator
(C) An active filter. (D) An instrumentation amplifier.
Ans: D
Q.6 Active loaded MOS differential circuit has
(A) high CMRR. (B) low CMRR.
(C) high delay. (D) high differential gain
Ans: D
Q.7 NPN transistor is not suitable for good analog switch
(A) IC −VCE characteristic curve pass directly through
(B) the device has very high input
(C) the device is asymmetrical with an offset voltage
(D) it has well defined transition frequency
Ans: C
Q.9 The order of input resistance in 741 OPAMP is
(A) 1 to 104      . (B) 103      .
(C) 105      . (D) 106      .
Ans: D
Q.10 The ratio of change in input offset voltage when variation in supply voltage is made is
(A) PSRR. (B) CMRR .
(C) transient response. (D) input offset voltage stability.
Ans: A
Q.11 The equiripple response filter is called _ , while maximally flat time delay
response is given by filter.
(A) Chebyshev, Bessel.
(B) Bessel, Chebyshev.
(C) Butter worth, Bessel.
(D) Chebyshev, Butter Worth.
Ans: D
Q.12 A notch filter is a
(A) Wide band pass filter.
(B) Narrow band pass filter.
(C) Wide band reject filter. (D) Narrow band reject filter.
Ans: D
Q.13 The problem faced by switched capacitor filters is
(A) aliasing (B) amplitude distortion
(C) slower roll off rate (D) longer time and phase delay
Ans: Only draw back with switched capacitor filters is that they generate more noise than
active filter circuits.
Q.14 For a 3-bit flash ADC, the number of comparators required are
(A) 5 (B) 9
(C) 7 (D) 3
Ans: C
Q.15 The typical quiescent power dissipation of low-power CMOS units is
(A) 1mW. (B) 0.5 mW.
(C) 2 nW. (D) 50 nW.
Ans: C
Q.16 The access times of MOSRAMS is approximately
(A) 35 ns. (B) 80 ns.
(C) 400 ns. (D) 20 ns.
Ans: Question seems to be invalid as it is not mentioned weather static or dynamic RAM
and access time varies by large magnitude from chip to chip.
Q.18 Active load is used in the collector of the difference amplifier of an
(A) To increase the output
(B) To increase the differential
(C) To handle large signals.
(D) To provide symmetry.
Ans: B
Q.23 For standard TTL logic circuits, the values of
(A) 0.8 V and 2.0 V.
(C) 0.4 V and 2 V.
Ans: D
VOL = 0.4 V & VOL= 0.4 & V
Q.25 In a sample and hold circuit the following statement is
(A) Sample time is much smaller than hold
(B) Aperture time is the delay between the time that the pulse is applied to the switch
and the actual time the switch
(C) Acquisition time is the time it takes for the capacitor to charge from one voltage to
another voltage.
(D) The voltage across the hold capacitor changes by 50% during hold
Ans: A
Q.26 The voltage between the emitter and collector of a silicon transistor when the transistor is
biased to be at the edge of saturation is:
(A) 5 volts. (B) 10 volts.
(C) 0.1 volts. (D) 0.3 volts.
Ans: D
VEOS = 0.3V
Q.27 The fastest switching logic family is
(A) CMOS. (B) TTL.
(C) DTL. (D) ECL.
Ans: D
Q.28 A 32 to 1 multiplexer has the following features.
(A) 32 outputs, one input and 5 control signals
(B) 32 inputs, one output and 5 control signals
(C) 5 inputs, one control signal and 32 outputs
(D) 5 inputs 32 control signals and one output
Ans: B
Q.29 The unity gain bandwidth of 741 OPAMP is typically
(A) 4 MHz. (B) 2 MHz.
(D) 6 MHz. (D) 1 MHz.
Ans: D
Q.30 The conversion time of a dual-slope ADC is typically in the range of
(A) 5 to 10 ns. (B) 10 to 100 ns.
(C) 100 to 200 ns. (D) 2 to 3 ns.
Ans: C
In dual slope low conversion time is not the primary concern.
Q.31 In a transistor switch, the voltage change from base-to-emitter which is adequate to
accomplish the switching is only about
(A) 0.2 V. (B) 0.4 V.
(C) 0.1 V. (D) 0.5 V.
Ans: D
0.5 V assuming silicon transistors.
Q.32 Worst case ECL noise margins are approximately
(A) 100 mV. (B) 50 mV.
(C) 250 mV. (D) 400 mV.
Ans: C
Noise margin = 250 mv.
Q.33 A certain multiplexer can switch one of 32 data inputs to its output. How many different
inputs does this MUX have?
(A) 30 data inputs & 5 select inputs.
(B) 32 data inputs and 4 select inputs.
(C) 32 data inputs and 5 select inputs.
(D) None of the above.
Ans: C
32 data inputs and 5 select input as (25=32).
Q.34 What J-K input condition will always set ‘Q’ upon the occurrence of the active clock
(A) J = 0, K = 0 (B) J = 1, K = 1
(C) J = 1, K = 0 (D) J = 0, K = 1
Ans: C
Q.35 Given a MOD-14 ripple counter using J-K flip-flops. If the clock frequency to the counter is
30 KHz, then the output frequency of the counter will be
(A) 2.2 KHz. (B) 30 KHz.
(C) 2.14 KHz. (D) 3.2 KHz.
Ans: C
2.14 KHz as clock frequency gets divided by n (n = no of mod).
Q.36 The open-loop voltage gain of 741 OPAMP is typically
(A) 40 dB. (B) 200 dB.
(C) 100 dB. (D) 70 dB.
Ans: C
Open loop gain = 105 (20 log 105 = 100 dB )
Q.37 How many comparators would a 12-bit flash ADC require?
(A) 4000 (B) 3095
(C) 4095 (D) 2512
Ans: C
Numbers of comparators for 12 bit flash ADC
= 2n-1
Q.38 Schottky TTL gates have propagation delay time of the order of
(A) 6 ns. (B) 5 ns.
(C) 2 ns. (D) 8 ns.
Ans: C
Schottky TTL gates have propagation delay of order of 2ns as the storage time delay is
removed in schottky transistor.
Q.46 The number of address bits needed to operate a 2K × 8-bit RAM are:
(A) 9 (B) 25
(C) 15 (D) 11
Ans: D
Q.47 A one-to-sixteen demultiplexer requires
(A) 2 select input lines. (B) 3 select input lines.
(C) 8 select input lines. (D) 4 select input lines.
Ans: D
As 1*16 Demux requires 4 (24 = 16) select lines to select one among the 16 outputs.
Q.48 The charge coupled devices are implemented using
(A) CMOS Technology (B) PMOS Technology
(C) MOS Technology (D) NMOS Technology
Ans: C
Q.49 Schottky diodes exhibit a storage time of approximately
(A) Zero sec. (B) 20 sec.
(C) 30 ns. (D) 32 ms.
Ans: C
30ns storage time is reduced due to metal-semiconductor junction.
Q.50 In an analog multiplier, if both the inputs are positive or negative then the multiplier is said
to be
(A) a two quadrant multiplier. (B) a one quadrant multiplier.
(C) a four quadrant multiplier. (D) a three quadrant multiplier.
Ans: C
Q.51 The large signal differential voltage amplification of the 741 OPAMP is typically about
(A) 100 V/mv. (B) 500 V/mv.
(C) 1000 V/mv. (D) 200 V/mv.
Ans: C
as Gain-Bandwidth product= 1 MHz
Q.52 If the input offset current and the average input bias current for an OPAMP are respectively
5nA and 30 nA, then the input bias currents at each input of the OPAMP are respectively
(A) 32.5 nA & 27.5 nA. (B) 22.5 nA & 30.2 nA.
(C) 10 nA & 16 nA. (D) 2.5 nA & 3.02 nA.
Ans: A
Thus input bias current at each input solving above two equations gives Ans (A)
Q.53 In a first-order low-pass active filter, if the values of the resistance and the capacitor used are
1.2 K  and 0.02μF respectively, then the cut-off frequency of the filter is
(A) 3.6 KHz. (B) 8.7 KHz.
(C) 8.2 Hz. (D) 6.63 KHz.
Ans: D
Q.54 A clock rate of one megahertz operating a 12-stage counter of a counter-type ADC would
need a maximum conversion time of approximately
(A) 3.2 ms. (B) 4.1 ms.
(C) 8 ms. (D) 7.1 ms.
Ans: A
Q.55 Typical propagation delay of an ECL circuit is
(A) 10 ns. (B) 5 ns.
(C) 1 ns. (D) 3.2 ns.
Ans: B
5 ns – fastest logic family.
Q.56 The number of states in its counting sequence that a ring counter consisting of ‘n’ flip-flops
can have is
(A) 2n − 1 (B) 2n−1
(C) n (D) 2n+1
Ans: C
n bit shift register connected as ring counter can count total N-states.
Q.57 The number of select input lines required by a 1-to-8 demultiplexer are
(A) Two. (B) One.
(C) Four. (D) Three.
Ans: D
1 to 8 Demux require 3 (8=23) select lines to select one output among 8.
Q.58 The Maximum binary number counted by a ripple counter that uses four FlipFlop’s is
(A) (0000)2
(C) (1111)2
(B) (1011)2
(D) (0101)2
Ans: C
as ripple counter with four FF’s will count 16 states from zero to fifteen.
Q.59 The cut-in voltage of the aluminium n-type Schottky diode is about
(A) 0.5 V. (B) 0.5 μV .
(C) 0.35 V. (D) 0.35 mV.
Ans: C
as the cut in voltage becomes half due to metal – sc function.
Q.60 The amplifiers in the sample and hold circuit are used to provide voltage amplification.
(A) True (B) False
Ans: B
Sample and hold circuit does not have amplifiers.
Q.61 In a Chebyshev filter of odd order, the oscillatory curve of the magnitude response does
not start from unity
(A) True (B) False
Ans: B
As the magnitude response starts from unity in chebyshev odd order filters.
Q.62 Due to its simple circuit structure, MOS circuitry is not so well suited for LSI
(A) True (B) False
Ans: B
Q.63 The bit storage cells in a RAM, when high speed is required make use of a BJT
(A) True (B) False
Ans: A
True as switching speed of BJT is high.
Q.64 An instrumentation amplifier should not have a high CMRR
(A) True (B) False
Ans: B
Instrumentation Amplifier amplifies the difference of the I/P signal.
Q.65 In a Chebyshev filter of even order, the oscillatory curve of the magnitude response starts
from unity
(A) True (B) False
Ans: B
Magnitude response of even order Chebyshev filter does not start from unity.
Q.66 As the gate voltage switches from a LOW voltage to a HIGH voltage, the N-MOSFET
will switch from a very LOW resistance to a HIGH resistance
(A) True (B) False
Ans: B
As the gate voltage switches from low voltage to high voltage. NMOS starts conducting and
it will switch from very high resistance to low resistance.
Q.67 The circuit for a DEMUX is basically the same as for a decoder, provided the decoder has
an enable input
(A) True (B) False
Ans: A
DEMUX & Decoder are same circuits with decoder has an enable input.



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