BSNL TTA (JE) MICROPROCESSORS 200 EXPECTED QUESTIONS PART TWO

THIS IS THE SAMPLE OF PART TWO 20 QUESTIONS
IN PART TWO TOTAL NO OF QUE IS 120 BECAUSE IF WE CONSIDER ONLY 100 QUE THEN SOME IMPORTANT QUE LEFT SO WE HAVE INCREASED NO OF QUE.
ANSWER-Correct answer is indicated by symbol (V) in options.
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1) On receiving an interrupt from an I/O device, the CPU
A [ ]) halts for a predetermined times
B [ ]) hands over the control of address bus and data bus to the interrupting device
C [ ]) branches off to the interrupt service routine immediately
D [v]) branches off to the interrupt serviceroutine after completion of the current instruction
2) The ALE line of 8085 microprocessor is used to
A [ ]) latch the output of an I/O instruction into an external latch
B [ ]) deactivate the chip-select signal from memory device
C [v]) latch the 8-bit of address lines AD0-AD7 into an external latch
D [ ]) find the interrupt enable status of the TRAP interrupt
3) The first operation performed in INTEL 8085 microprocessor after RESET is
A [v]) instruction fetch from 0000H
B [ ]) memory read from the location 0000H
C [ ]) instruction fetch from location 8000H
D [ ]) stack initialization
4) The 8085 microprocessor will enter into INA cycle after recognition of
A [ ]) any interrupt
B [ ]) TRAP only
C [v]) INTR only
D [ ]) RST 7.5,RST 6.5 & RST 5.5 only
5) Which of the following lists the interrupt in decreasing order of priority?
A [ ]) TRAP, RST 5.5, RST 6.5, RST 7.5, INTR
B [ ]) INTR, TRAP, RST 7.5, RST 6.5, RST 5.5
C [v]) TRAP, RST 7.5, RST 6.5, RST 5.5, INTR
D [ ]) RST 7.5, RST 6.5, RST 5.5, TRAP, INTR
6) The interrupt vector address for TRAP is
A [ ]) 0000H
B [v]) 0024H
C [ ]) 0018H
D [ ]) 002CH
7) In order to reset the carry without affecting the accumulator content one has to use,
A [ ]) SUB A
B [ ]) XRA A
C [v]) ORA A
D [ ]) CMC
8) Maximum number of I/O that can be addressed by the INTEL 8085 is
A [ ]) 65536
B [ ]) 285
C [ ]) 512
D [v]) 256
9) The microprocessor may be made to exit from HALT state by asserting
A [ ]) RESTART
B [ ]) any of the five interrupt lines
C [ ]) READY line
D [v]) RESTART or any of the five interrupt lines or HOLD line
10) The 8085 microprocessor enters into bus idle machine cycle whenever
A [ ]) INTR interrupt is recognized
B [v]) RST 7.5 is recognized
C [ ]) DAD RP instruction is executed
D [ ]) none of the above
11) During OPCODE fetch the state of S0 and S1 is
A [ ]) 00
B [ ]) 01
C [ ]) 10
D [v ]) 11
12) After RESET 8255 will be in
A [v]) mode 0; all ports are input
B [ ]) mode 0; all ports are output
C [ ]) mode 2
D [ ]) unchanged condition
13) The microprocessor issues ALE during first T-state of
A [ ]) fetch cycle only
B [ ]) memory READ cycle only
C [ ]) memory WRITE cycle only
D [v]) every machine cycle
14) The content of the A15-A8 (higher order address lines) while executing “IN 8-bit port
address” instruction are
A [v]) same as the content of A7-A0
B [ ]) irrelevant
C [ ]) all bits reset (i.e. 00H)
D [ ]) all bits set (i.e. FFH)
15) Which one of the following ICs is used to interface keyboard and display?
A [ ]) 8251
B [v]) 8279
C [ ]) 8259
D [ ]) 8253
16) Which one of the following interrupt is only level triggering?
A [ ]) TRAP
B [ ]) RST 7.5
C [v]) RST 6.5 and RST 5.5
D [ ]) RST 6.5
17) Which one of the following instruction may be used to clear the accumulator content
irrespective of its initial value?
A [ ]) CLR A
B [ ]) ORA A
C [v]) SUB A
D [ ]) MOV A, 00H
18) The execution of RST n instruction causes the stack pointer to
A [ ]) increment by two
B [v]) decrement by two
C [ ]) remain unaffected
D [ ]) none of the above
19) The stack is nothing but a set of
A [ ]) reserved ROM address space
B [v]) reserved RAM address space
C [ ]) reserved I/O address space
D [ ]) none of the above
20) S0 and S1 pins are used for
A [ ]) serial communication
B [v]) indicating the processor’s status
C [ ]) acknowledging the interrupt
D [ ]) none of the above
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BSNL TTA ONLINE TEST RESULT CURRENT AFFAIRS JULY 2
RESULT BSNL TTA(JE) ONLINE TEST SERIES 2

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